1. Field
The invention relates to coupling electronic components and, in one aspect, to techniques for performing test and burn-in procedures on integrated circuit devices prior to their packaging, preferably prior to the individual devices being singulated from a wafer.
2. Background
Individual integrated circuit devices (dies) are typically produced by creating several identical devices on a semiconductor wafer, using known techniques of photolithography, deposition, and the like. Generally, these processes are intended to create a plurality of fully-functional integrated circuit devices prior to singulating (severing) the individual dies from the wafer. In practice, however, certain defects in the processing of the wafer inevitably lead to some of the dies being “good” (fully-functional) and some of the dies being “bad” (partially-functional or non-functional). It is generally desirable to be able to identify which of the plurality of dies on a wafer are good dies prior to their packaging, and preferably prior to their being singulated from the wafer. To this end, a device or a wafer “tester” or “prober” may advantageously be employed to make a plurality of discrete pressure connections to a like plurality of discrete connection pads (bond pads) on the dies. In this manner, the des can be tested and exercised prior to packaging, and preferably, prior to singulating the dies from the wafer.
A die or a plurality of dies on a wafer may be tested using an automated test system. Such a test system usually includes a processor that executes a test program engineered for testing devices (dies) under test (“DUTs”). A “probe card assembly” receives the test data from the processor and delivers it to locations in the DUTs. Typically, a plurality of probe elements are connected to the probe card assembly to effect pressure connections to respective bond pads of DUTs to effectuate the testing.
One type of probe card assembly includes a probe card. Probe cards are typically conventional circuit board substrates (e.g., of epoxy-impregnated fiberglass material) formed as circular rings, with hundreds of probe elements (needles) bonded to, and extending from an inner periphery of, the ring. Circuit modules and conductive traces (lines) of preferably equal lengths, are associated with each of the probe elements.
A second representative type of probe card assembly is described in commonly-owned, U.S. Pat. No. 5,974,662 issued Nov. 2, 1999, titled “Method of Planarizing Tips of Probe Elements of a Probe Card Assembly,” and U.S. Pat. No. 6,050,829 issued on Apr. 18, 2000, titled “Making Discrete Power Connections to a Space Transformer of a Probe Card Assembly,” each incorporated herein by reference. In one embodiment, the probe card assembly includes as its major functional components a probe card, an interposer, and a space transformer. The probe card is a circuit board substrate having terminals arranged about an inner periphery at a suitable pitch such as a 100 mil pitch.
To reduce the contact pitch of the probe card to a pitch of a DUT, a space transformer may be utilized. A typical space transformer, for example as described in U.S. Pat. No. 6,050,829, includes a suitable circuitized substrate, such as a multilayer ceramic substrate having a plurality of terminals disposed on opposites sides thereof. Interconnection elements, such as resilient interconnection elements described in the referenced, commonly-owned documents are used to couple the space transformer to the probe card and to a DUT. To couple to the probe card, the contact pads and/or interconnection elements are disposed at the pitch of the corresponding pads of the probe card (e.g., 100 mils), and the plurality of contact pads and/or interconnection elements to be coupled to a DUT may be disposed at a finer (closer) pitch of, for example, 50 mils, with ends of the interconnection elements coupling to contacts of the DUT at possibly an even finer pitch (e.g., a 10 mil pitch).
Between the space transformer and the probe card, an interposer may be employed to provide dimensional stability to the probe card assembly and adjust the planarity of the assembly in a Z-dimension to improve the electrical contact between the assembly and DUTs. One interposer is, for example, and as described in U.S. Pat. No. 5,974,662, a dielectric substrate having interconnection elements, including any of the resilient interconnection elements noted above, mounted to and extending from opposite sides of the substrate. The pitch of the interconnection elements is selected to correspond to the pitch of the probe card contact pads and the space transformer contact pads, respectively.
As described above, a typical probe card has hundreds or thousands of probe elements or terminals about an inner periphery and wired to conductive traces through the probe card to terminals. Such terminals may be disposed along an outer periphery of the probe card ring. Typically, conductive probe pins, such as “pogo pins,” electrically connect these terminals to host equipment such as a processor that executes a test program through a test head and associated circuitry.
One concern to designers of probe card assemblies is that to get from the pin electronics of the host equipment to the probe tips on the probe card, the signals must travel through a multi-element signal path (e.g., pogo pins, terminals, traces, etc.). These various elements have physical and electrical performance limitations that adversely affect conventional tester technology. For example, the pogo pins and their terminal coupling have certain known performance limitations which are addressed by matching pad capacitance and impedance to some arbitrary values. The probe card board material represents a further performance limitation in that the loss tangent of typical FR4 fiberglass material is such that even a few inches of this material in the signal path can represent significant attenuation and signal distortion.
Controlling impedance characteristics (capacitance, inductance, and contact resistance) and minimizing cross-talk between a multiplicity of signals, typically several hundreds, from the tester pin electronics to the device under test microcircuit represents a significant technical challenge. What is needed is improved tester technology that reduces the performance limitations of the conventional tester technology.